Samsung Surpasses 10nm Memory Threshold With First Functional Single-Digit DRAM Die

Samsung Electronics has successfully produced a functional working die for its 10a-class DRAM, representing the first time the semiconductor industry has breached the 10-nanometer threshold in memory fabrication. According to reports from The Elec and TrendForce, the company confirmed the operational status of the die during device characterization testing conducted in March 2026.

This “10a” node marks a pivotal shift in the memory scaling sequence, moving beyond the 10nm-class limit that previously defined the 1x through 1d generations. With circuit linewidths estimated between 9.5nm and 9.7nm, this development suggests that physical scaling can continue even as traditional lithography approaches its theoretical limits. For the global technology sector, this breakthrough is critical because it addresses the urgent need for higher memory density and reduced power consumption required by intensive artificial intelligence workloads.

Structural Evolution Through 4F Square Cell Design

To achieve the sub-10nm threshold, Samsung has transitioned from the long-standing industry-standard 6F square structure to a new 4F square cell design. This architectural shift fundamentally changes how memory cells are arranged on the silicon wafer, moving from a rectangular orientation to a more compact square layout. According to TrendForce, the 4F square structure utilizes a 2F x 2F footprint, which allows for a significantly more efficient use of available space.

This structural change enables a 30% to 50% increase in cell density within the same die area compared to previous generations. By shrinking the area required for each individual memory cell, Samsung can fit more gigabits of storage onto a single chip without increasing the physical size of the component. This density improvement is essential for meeting the capacity demands of modern data centers and high-performance computing environments.

Alongside the 4F square design, Samsung has implemented Vertical Channel Transistors (VCT) as a primary manufacturing process for the 10a node. Traditional DRAM designs rely on horizontal transistors, but as dimensions shrink, these horizontal components face increased electrical interference and physical space constraints. The VCT approach reorients the transistor vertically, allowing the channel to stand upright rather than lying flat across the substrate.

The adoption of vertical transistor orientation provides a distinct operational advantage by drastically reducing the physical footprint of the memory cell’s controlling logic. This verticality allows for shorter interconnects and less crowding between adjacent cells, which helps maintain signal integrity at single-digit nanometer scales. Analysis of this transition suggests that vertical structures are no longer an experimental choice but a necessary evolution to bypass the physical congestion of planar layouts.

The implementation of VCT also facilitates better control over the electrical current within each cell. By moving to a three-dimensional transistor profile, Samsung can maintain higher performance levels while minimizing the heat generation typically associated with extreme miniaturization. This structural foundation is expected to serve as the blueprint for the next several years of Samsung’s DRAM development.

Material Advancement via IGZO Channel Implementation

A critical component of the 10a node’s success is the replacement of traditional silicon with Indium Gallium Zinc Oxide (IGZO) as the primary channel material. As circuit linewidths drop below 10nm, silicon channels often suffer from increased leakage current, where electricity escapes the intended path and leads to data corruption or excessive power draw. TrendForce reports that Samsung’s use of IGZO is specifically designed to mitigate these scaling-related instabilities.

IGZO is a thin-film transistor material that offers significantly lower off-state leakage compared to standard silicon. This characteristic improves data retention within the highly scaled cells, allowing the DRAM to hold information longer between refresh cycles. By reducing the frequency of refresh operations, the memory system can lower its overall power consumption, which is a major operational cost for large-scale AI infrastructure.

The shift to IGZO represents a broader trend in the semiconductor industry where material science breakthroughs are becoming mandatory as lithography reaches its physical limits. When transistors are packed as tightly as they are in the 10a node, the physical properties of silicon are no longer sufficient to prevent electrical interference. Analysis indicates that the introduction of oxide semiconductors like IGZO provides the necessary electrical isolation to make single-digit nanometer nodes commercially viable.

Furthermore, the integration of IGZO allows for better thermal stability during high-speed data operations. As memory chips are pushed to higher clock speeds to keep pace with modern processors, managing the heat generated by billions of transistors becomes a primary engineering challenge. The material properties of IGZO help maintain consistent performance even under the thermal stress of continuous AI training and inference tasks.

Integration into Pangea v2 and CXL Ecosystems

Samsung is already demonstrating how these sub-10nm advancements will be utilized at the system level, recently presenting its “Pangea v2” memory system at the IEEE. This system is built on the Compute Express Link (CXL) 2.0 standard, which was introduced in 2020 by a consortium including Intel and NVIDIA. Pangea v2 is designed to overcome the “memory wall” where processor speeds outpace the ability of traditional memory architectures to deliver data.

Performance metrics for the Pangea v2 system show a 10.2× higher data transfer performance compared to conventional interconnect methods like Remote Direct Memory Access (RDMA). Additionally, Samsung reported that the system reduces data bottlenecks—a persistent challenge in traditional server architectures—by as much as 96%. These gains are achieved by using a CXL-based memory pool that allows for more direct and efficient communication between the CPU and memory modules.

The Pangea v2 architecture connects 22 CXL DRAM modules (CMM-D) into a single shared memory resource, enabling multiple servers to access up to 5.5TB of memory simultaneously. This pooling capability is a departure from traditional server designs where memory is strictly tied to a specific processor. According to reports from Hankyung, Samsung collaborated with semiconductor designer Marvell and AI infrastructure firm Liquid AI to develop this high-performance infrastructure.

The arrival of sub-10nm DRAM chips is expected to specifically populate these high-capacity CXL pools to meet the extreme density requirements of AI infrastructure. Because 10a-class DRAM offers higher density per module, Samsung can reach the 5.5TB threshold using fewer physical slots or significantly increase the total capacity of the pool without expanding the server’s physical footprint. This synergy between chip-level miniaturization and system-level interconnects like CXL is designed to provide the massive memory bandwidth required for next-generation generative AI models.

By integrating 10a-class DRAM into CXL systems, Samsung addresses the need for “memory expansion,” where servers can add memory capacity independently of the CPU’s built-in memory controllers. This flexibility allows data center operators to scale their resources more granularly. The combination of 4F square density and CXL efficiency positions the 10a node as a foundational technology for the post-HBM (High Bandwidth Memory) era.

Commercialization Timeline and 3D DRAM Transition

While the working die has been confirmed, the path to consumer availability follows a multi-year manufacturing roadmap. Samsung plans to complete the full development of the 10a DRAM node by 2026. This will be followed by a rigorous quality testing phase in 2027 to ensure the chips meet the reliability standards required for enterprise and data center use. Mass production is currently targeted for 2028, according to reports from The Elec.

Samsung’s roadmap indicates that the 4F square cell and VCT structures will be applied across three distinct generations: 10a, 10b, and 10c. This suggests that the company intends to refine this specific architecture over several years to maximize its yield and performance characteristics. However, the industry expects a major shift starting from the 10d node, where Samsung plans to transition to 3D DRAM, which stacks memory cells vertically to continue scaling beyond the limits of single-layer wafers.

The transition from a working die in characterization to high-volume manufacturing (HVM) involves significant logistical and engineering hurdles. Moving a new material like IGZO and a new structure like VCT into a mass production environment requires the calibration of thousands of lithography and etching steps to ensure uniformity across millions of units. Analysis suggests that the 2028 target for mass production provides the necessary window to solve the yield issues often associated with introducing two major technological shifts—new materials and new structures—simultaneously.

This roadmap highlights Samsung’s strategy to bridge the gap between current planar DRAM and the future of 3D memory. By perfecting VCT and 4F square designs now, the company establishes the manufacturing expertise needed for vertical stacking. The 10a node serves as the critical testing ground for the technologies that will eventually define the 3D DRAM era.

Market Positioning and the Race for Next-Gen Memory

The breakthrough in sub-10nm DRAM places Samsung in a competitive position as the industry shifts its focus toward “post-HBM” technologies. While High Bandwidth Memory has dominated the AI market recently, CXL is emerging as the next major battleground for memory makers. According to Hankyung, industry sources believe CXL will be the primary driver for memory growth as data centers look for more efficient ways to manage massive datasets.

Samsung’s progress is being closely watched alongside its primary competitors, SK Hynix and Micron. SK Hynix is currently preparing to sample its next-generation HBM4E memory and has already validated its first-generation CXL 2.0 products in 2025. Meanwhile, Micron entered the CXL race in 2024 with the unveiling of its own specialized modules. The competition is no longer just about raw speed, but about how effectively memory can be pooled and shared across complex AI networks.

Samsung’s lead in achieving a functional sub-10nm die may provide a significant advantage in this CXL battleground. Higher density chips allow Samsung to offer CXL modules with greater capacity than competitors using older 10nm-class nodes. Analysis suggests that if Samsung can successfully transition the 10a node to mass production by 2028, it could set the standard for the density and power efficiency required by the next generation of AI accelerators and server platforms.

The race for next-generation memory is increasingly defined by who can best integrate chip-level innovations with system-level standards. Samsung’s simultaneous advancement in sub-10nm fabrication and CXL system integration indicates a strategy aimed at capturing the entire AI memory value chain. As SK Hynix and Micron advance their own roadmaps, the ability to deliver functional, single-digit nanometer silicon remains a key differentiator in the high-end semiconductor market.

The successful production of a 10a-class DRAM working die marks a definitive end to the 10nm-class era and signals the beginning of a new phase in semiconductor scaling. By combining 4F square architecture, Vertical Channel Transistors, and IGZO materials, Samsung has addressed the physical and electrical barriers that threatened to stall memory progress. This breakthrough not only extends the life of DRAM scaling but also provides the high-density foundation necessary for the Pangea v2 system and the broader CXL ecosystem. As the industry moves toward 2028, the successful commercialization of this node will likely determine Samsung’s leadership position in the transition to 3D DRAM and advanced AI interconnects.